This application is related to Japanese Patent Applications Nos. 2001-275418 and 2002-168828, filed on Sep. 11, 2001 and Jun. 10, 2002 whose priorities are claimed under 35 USC xc2xa7119, the disclosures of which are incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to a heterojunction bipolar transistor. More particularly it relates to a heterojunction bipolar transistor serving as a semiconductor device for amplifying a high-frequency electric power such as a microwave band, a millimeter wave band and the like, and a production process therefor.
2. Description of Related Art
Heterojunction bipolar transistors (HBTs) which utilize heterojunction of compound semiconductors and use, for an emitter layer, a semiconductor whose forbidden band gap energy is larger than that of a base layer can provide a high current gain, because reverse injection of a minority carrier from the base layer to the emitter layer is suppressed and the injection efficiency of a carrier to the emitter layer improves. Also since the impurity concentration in the base layer can be raised to reduce the resistance of the base layer, the thickness of the base layer can be decreased to shorten transit time for the carrier to pass through the base layer. Thereby high-frequency characteristics can be improved.
With development of mobile communication equipment including mobile phones, there is a demand for higher-power, higher-efficient high-frequency amplifier devices, and the HBTs are greatly expected.
As other various devices, to reduce parasitic resistance and parasitic capacitance is a basic technique for improving characteristics of the HBTs. Criteria indicating the high-frequency characteristics of the HBTs include a cut-off frequency fT and a maximum oscillated frequency fmax, which are represented by the following formula:
fmax=(fT/8xcfx80RbCc)1/2xe2x80x83xe2x80x83(1)
wherein, Rb is a base resistance and Cc is a collector capacitance. If fT is constant, fmax can be increased by reducing the collector capacitance Cc. The collector capacitance Cc is represented by the sum of an intrinsic collector capacitance Ci and a parasitic collector capacitance Cex as shown by the following formula:
Cc=Ci+Cexxe2x80x83xe2x80x83(2).
The intrinsic collector capacitance Ci is determined by the structure of a semiconductor layer, while the parasitic collector capacitance Cex is determined by the configuration of a device. Therefore, the collector capacitance Cc can be reduced by a production process of the configuration.
In order to reduce the parasitic collector capacitance, IEEE Trans. Electron Devices ED34 pp. 2571-2577 proposes a technique of depleting an external collector layer by implanting hydrogen or oxygen ions into the external collector layer under an external base electrode. However, by this method, the base resistance Rb increases due to damage to the base layer caused by ion implantation, and as a result, it is difficult to improve fmax.
Other methods of etching away a collector layer under an external base layer in a lateral direction are disclosed in Japanese Unexamined Patent Publications Nos. HEI 3(1991)-10839, HEI 8(1996)-64610 and HEI 9(1997)-246280, and GaAs IC Symposium 1995 Tech. Digest pp. 160-170.
By the methods, the parasitic collector capacitance can be reduced since a void is formed under the external base layer.
However, the above-mentioned methods have the effect of reducing the parasitic capacitance, but on the other hand, the yield in a process for forming the base electrode and a lead electrode therefor is poor and the reliability of devices is questionable.
The present invention is to solve the above-described problems of the prior art, and an object thereof is to provide a reliable heterojunction bipolar transistor with a reduced parasitic collector capacitance which can be produced in a good yield, and a process for producing the heterojunction bipolar transistor.
The present invention provides a heterojunction bipolar transistor comprising
a collector layer of a first conductivity type,
a base layer of a second conductivity type, and
an emitter layer of the first conductivity type, which are formed on a semiconductor substrate in this order, and further
a collector electrode directly or indirectly connected to the collector layer,
a base electrode directly or indirectly connected to the base layer, and
an emitter electrode directly or indirectly connected to the emitter layer,
wherein a semiconductor protecting layer is formed on the base layer and extended outside an edge of the base layer,
the base electrode is formed on the semiconductor protecting layer, and
at least a region under the semiconductor protecting layer is filled with an organic insulator.
The present invention also provides a process for producing a heterojunction bipolar transistor comprising the steps of:
forming at least a collector layer, a base layer, a semiconductor protecting layer and an emitter layer on a semiconductor substrate in this order;
carrying out an emitter mesa etching to etch away a part of the emitter layer to the surface of the semiconductor protecting layer;
masking the emitter layer and a part of the semiconductor protecting layer, etching away an unmasked part of the semiconductor protecting layer, and continuously etching the base layer and the collector layer so that the area of the base layer and the collector layer becomes smaller than the resulting semiconductor protecting layer; and
applying a polyimide precursor having a positive-type photosensitivity onto the resulting semiconductor substrate, patterning and thermally treating the polyimide precursor, thereby forming an organic insulator so as to fill at least a region under the semiconductor protecting layer.
The present invention further provides a process for producing a heterojunction bipolar transistor comprising the steps of:
forming a sub-collector, an etching stopper layer, a collector layer, a base layer, a semiconductor protecting layer and an emitter layer on a semiconductor substrate in this order;
carrying out an emitter mesa etching to etch away a part of the emitter layer to the surface of the semiconductor protecting layer;
masking the emitter layer and a part of the semiconductor protecting layer, etching away an unmasked part of the semiconductor protecting layer, and continuously etching the base layer and the collector layer to the etching stopper layer so that the area of the base layer and the collector layer becomes smaller than the resulting semiconductor protecting layer and
forming a mask to cover all the resulting semiconductor protecting layer and etching away an unmasked region of the etching stopper layer.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.